The present disclosure generally relates to wireless communication and more specifically to digital down conversion (DDC) and decimation filtering.
Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
Digital down conversion refers to converting a digitized radio frequency (RF) signal that is centered at an intermediate frequency (fIF) to a baseband signal centered at a baseband frequency (e.g., zero frequency). FIG. 1 depicts a conventional system 100 for digital down conversion and decimation filtering. A radio frequency signal is received at an analog-to-digital converter (ADC) 102. The radio frequency signal is digitized into a digital signal SADC. ADC 102 samples the radio frequency signal at a sampling rate fs. The resulting digital signal is centered at intermediate frequency fIF. The intermediate frequency fIF is typically not at a baseband frequency required for processing by a baseband processor. System 100 performs a digital down conversion to down convert the digital signal SADC to the baseband frequency.
FIG. 2A illustrates the down conversion. At 202, the digital signal SADC is centered at the intermediate frequency. After down conversion, the digital signal SADC is shifted to the baseband frequency, which may be at or near zero. However, in the down conversion, replicas of the signal are also shifted to higher frequencies, such as a frequency 2fIF. The replicas need to be removed through a decimation filter. FIG. 2B shows a decimation of a higher frequency component of the signal (e.g., a replica) while leaving a signal at the baseband frequency.
Referring back to FIG. 1, a mixer 104a, a mixer 104b, and a local oscillator (LO) 106 are used to down convert the digital signal SADC to the baseband frequency in a digital down conversion stage 103. Local oscillator 106 inputs a cosine signal into mixer 104a. Also, the cosine signal is shifted by 90 degrees to an inverted sine wave and input into mixer 104b. The output of mixer 104a is a down converted into an in phase signal, IDN, and the output of mixer 104b is down converted into a quadrature signal, QDN. In down converting the digital signal SADC, replicas of the digital signal are also generated at higher frequencies. The replicas need to be decimated, thus leaving a baseband in phase (I) signal and a baseband quadrature (Q) signal at the baseband frequency.
A decimation stage 107 separately decimates the in phase signal IDN and the quadrature signal QDN. For example, the in phase signal IDN is decimated using a first decimation filter 108a that includes a first low pass filter (I_LPF) 110a and down sampler 112a, and the quadrature signal QDN is decimated using a second decimation filter 108b that includes a second low pass filter (Q_LPF) 110b and second down sampler 112b. The resulting output of decimation stage 107 is an I signal and a Q signal at the baseband frequency.
Decimation stage 107 includes separate decimation filters 103a and 103b. For example, a first low pass filter 110a and a down sampler 112a are used to decimate the I signal, and a second low pass filter 100b and a second down sampler 112b are used to decimate the Q signal. Using separate decimation filters 103a and 103b to decimate IDN and QDN generally requires a lot of power and uses a lot of area